1. To develop Deep Neural Networks (DNNs) to classify different diseases from physiological signals.
  2. To implement the software DNNs in hardware using TSMC 65nm design technology.
  3. To design digital circuits that follow hardware-software Co-Design methodology and resemble stacked LSTMs to classify diseases from raw ECG signals with minimal preprocessing.
  4. Hardware security: To design software models that can be used to classify Integrated Circuits (ICs) based on Intrinsic Nonlinearity (INL) associated with each IC during fabrication process. Developing trojan models that can be used in improving the security of hardware design in ML chips.
  5. Analog and mixed signal integrated circuits for embedded machine learning: To develop ultra low power circuits for performing on-chip Machine Learning (ML) with high classification accuracies. A strong focus is in developing ML chips with high accuracy and low power consumption in nJ/Classification ranges, more than 100x lower power than conventional digital AI processors.